There are a variety of power amplifiers that can be classified into two groups: classical, non-switching amplifiers such as class A, class B, class AB, class C, and switching-mode amplifiers such as class D, class E, and class F. A non-switching amplifier has its active elements operating in the linear region for a specific predetermined conduction angle and generates an amplified output signal that is proportional to the input signal or a portion of the input signal. Non-switching amplifiers have a relatively low power-added efficiency (PAE) since a relatively large portion of the conduction angle is in the linear region of the transistor resulting in power dissipation, whereas switching amplifiers can achieve theoretical efficiency of 100%. Since portable and wearable electronic devices have gained popularity, the demand for smaller, lighter, and more power efficient electronic devices has also increased. The fast transition (square wave) needed to reduce transistor power dissipation in switching-mode amplifiers also results in high frequency content present in the harmonics of the signal. The harmonics may exceed out-of-band spurious emission limits set by standard regulatory agencies, such as the U.S. Federal Communications Commission (FCC) or ETSI.
FIG. 1A is a block diagram of an ideal class-D amplifier 100. Class-D amplifier includes a cascade-connected inverting amplifier stages 101, 102, and 103. The radio frequency (RF) input signal RFin is a square wave having a duty cycle of 50%. A duty cycle of 50% is referred to a square waveform having the voltage high (“1”) during half of each cycle and the voltage low (“0”) during the rest of the duty cycle. FIG. 1B is a functionally equivalent circuit of FIG. 1A. Each inverting amplifier stage includes a p-channel metal oxide semiconductor (PMOS) device and an n-channel metal oxide semiconductor (NMOS) device connected in series between a power supply VDD and ground. Ideal class-D amplifier 100 operates by switching between fully-on and fully-off. When in the fully-on mode, the current through the power transistor is at a maximum, but the voltage is at a minimum, so that the power dissipation is minimal. When in the fully-off mode, the voltage across the power transistor is at a maximum, but the current is at a minimum, so that the power dissipation is also minimal.
FIG. 1C is a circuit diagram illustrating parasitic capacitance in an inverting amplifier stage. Referring to FIG. 1C, the inverting amplifier stage has an input parasitic capacitance C1 between the gate and ground (comprised of the PFET gate to drain, PFET gate to source, and NFET gate to drain, and NFET gate to source, capacitances), a parasitic capacitance C2 between the source and drain of the PMOS transistor, and a parasitic capacitance C3 between the drain and source of the NMOS transistor. In operation, the inverting amplifier stage generates an output signal RFout and applies the RFout signal to an antenna for transmission. Because the parasitic capacitance C1, C2, and C3 are charged as a result of the input signal and as a result of the one of the PMOS or NMOS being “on”, the parasitic capacitances cause delay in the rise and fall time of the signal. Since the delay in the rise time may not equal the delay in the fall time, pulse width distortion can occur, and is likely to occur in any practical design, particularly over process and temperature.
FIG. 1D is a graph illustrating rise and fall times of signals traversing across an inverting amplifier stage. As shown in FIG. 1D, due to the charging and discharging of the parasitic capacitances, signals at the output of an inverting amplifier stage have slow rising and falling edges that consume relatively large power during the slow transition when both transistors are conducting. Because the electron mobility between the PMOS and NMOS transistors are different, the rise and fall times of the edges may mismatch. The mismatch of the rise and fall times of the edges cause a distortion in the duty cycle that causes even-order harmonics that are normally not present to appear. The second harmonic is the most problematic of the even-order harmonics and is often singled out for emphasis.
FIG. 2A is a graph illustrating an ideal square wave with 50% duty cycle. FIG. 2B is a graph illustrating the harmonics produced by the ideal square wave with 50% duty cycle. As shown in FIG. 2B, the odd harmonics, i.e., third harmonic H3, fifth harmonic H5 and seventh harmonic H7 exceed the FCC emission limit. One way of solving the harmonics emission problem is to add a low-pass filter and a band-stop (notch) filter at the output of the amplifier to filter out any unwanted harmonics. FIG. 2C is graph illustrating the harmonics passing through a low-pass filter with a notch (band-pass filter) at the third harmonic H3 to satisfy the FCC emission limits.
FIG. 3A a graph illustrating a square wave with pulse width distortion, i.e., the duty cycle is other than 50%. Please note that the drawings are not necessarily drawn to scale and the numerical values provided herein are for explanation purposes. Referring to FIG. 3A, output signals may be 40% (in praxis more close to 48%) of the time and 0V 60% (in praxis more close to 52%) of the time. FIG. 3B is a graph illustrating the harmonics produced by the square wave with a duty cycle other than 50%, while the fundamental frequency remains unchanged. As shown in FIG. 3B, a duty cycle other than 50% will produce even-order harmonics H2 that exceed the FCC emission limit. As shown in FIG. 3C, it is the 2nd harmonic that is most problematic due to its close proximity to the fundamental. One way to reduce the second harmonic is to add an extra band-stop (notch) filter at the output of the amplifier targeting the 2nd Harmonic. Such complicated filters are normally not feasible to be integrated with the amplifier in a same integrated circuit. Further, such filter, whether on or off chip, will introduces power loss to the fundamental frequency. FIG. 3C is graph illustrating the harmonics passing through a low-pass filter with a notch filter tuned to the third harmonic H3. As shown in FIG. 3C, higher-order harmonics (e.g., H4, H5, H6, etc.) are well attenuated by the low-pass filer, but the second harmonic is relatively close to the fundamental frequency, so that adding a notch at H2 may also affect the frequency response of the fundamental frequency, i.e., the notch filter targeting the second harmonic H2 may exhibit some attenuation at the fundamental frequency and adversely degrade the output power and efficiency.
For class-D amplifiers used for audio applications, the audio signal is modulated onto the high frequency square wave by pulse-width modulation. After efficient amplification of the pulse-width modulated square wave at the fundamental switching frequency, the fundamental switching frequency as well as all harmonics of the switching frequency can be easily removed through a low-pass filter, leaving the audio signal of interest. Since the switching frequency and harmonics are very far from the audio frequency, a low-pass filter is sufficient. Additional notches targeting specifics harmonics is not needed in the audio application. In the case of the proposed RF class-d amplifier, the fundamental switching frequency is the frequency of interest (to be amplified and transmitted via the antenna). The desired information is modulated by phase or frequency modulation which preserves the ideal 50% duty cycle (the switching frequency is not pulse-width modulated, but rather phase or frequency modulated). Therefore the filtering requirements are quite different, since only the harmonics of the fundamental must be removed, but not the fundamental switching frequency itself. Unfortunately, such a low-pass filter cannot be realized at a reasonable cost in radio frequency (RF) applications due to the required high Q-factor. Off-chip SAW or BAW filters add cost and significant loss of 1 dB or more.
Therefore, there is a need to control the rise and fall times at the output signals of a (frequency or phase modulated) class-D amplifier to prevent the square wave from deviating from the 50% duty cycle that is the source of the second harmonic.